Introduction Monitoring and prediction of hydrologic droughts and determining the onset and duration of drought spells have an important role in water resources management and planning to reduce the adverse effects of drought. In the present study the characteristics of hydrological drought in daily discharge time series from 20 hydrometric stations in Golestan Province have been analyzed. Matherials & Methods: In this study, the onset and end of drought periods, mean discharge, effective discharge and threshold level were calculated and then sequence number of 1 to 30-month durations were determined. According to the results of POWER Laws ANALYSIS, the intensity and duration patterns of hydrological drought periods were distinguished. The results specified an inverse relationship between the intensity and duration of wet and dry spells. The highest severity of dry spell is related to Nodeh station (Line slope=-0. 26) and the highest intensity of wet spell was observed in Ramian station (Line slope =-0. 28) which indicated the stability of dry and wet river flow regimes in Nodeh and Ramian stations. Also, the longest durations of dry and wet periods were determined for the Aghghala (32. 89) and Basirabad (16. 29) stations, respectively, which represents the average maximum probable durations. Discussion of Results & Conclusions: The proximity, closeness to a straight line or parallel lines without intersection proved the homogeneity regime of wet-dry spells in the Gorganroud watershed. ANALYSIS of wet-dry spells using the POWER Laws technique provides a basis to determine the flow regime, severity and duration of hydrological drought.

Now days, sharing data in communication systems and computers require high levels of Information security. Side channel attack is one of the methods which it is applied to attack cryptographic systems such as smart cards. In this paper, a new approach for countermeasuring cryptographic algorithms has been proposed and implemented on FPGA. The scheme is based on using Phase Locked Loop in AES algorithm which by disturbing POWER consumption pattern and execution time of different rounds, the resistance of the algorithm against POWER attack has been increased. Masking and hiding technique has been used to protect the encryption key. Overall, the proposed method has been simulated within TSMC 65nm technology platform and outstanding success has been obtained; in applying the technique to AES, the overhead was 13% in CMOS area, 15% in POWER consumption, 2% decrease in working frequency while finding the key became difficult for attackers. In addition, the proposed method has been implemented on FPGA and satisfactory results have been obtained for an acceptable number of samples of the POWER trace.

DIFFERENTIAL POWER ANALYSIS ((DPA)) implies measuring the supply current of a cipher-circuit in an attempt to uncover part of a cipher key. Cryptographic security gets compromised if the current waveforms obtained correlate with those from a hypothetical POWER model of the circuit. In recent years, the security of the Advanced Encryption Standard (AES) against (DPA), has received considerable attention. This paper presents a practical implementation of advanced encryption standard (AES-128) algorithm combined with a simple yet effective masking scheme to protect it against DIFFERENTIAL and correlation POWER ANALYSIS attacks. The proposed masking scheme has advantages of easy software implementation and lower memory requirement compared to conventional first-order masking technique. In addition, it is robust against both first and second-order DIFFERENTIAL POWER ANALYSIS. The experimental results and also the results of Welch’ s T-Test statistical ANALYSIS demonstrate that the proposed scheme has less information leakage than other existing conventional first-order masking schemes.

Current DIFFERENTIAL based wide area protection (WAP) has recently been proposed as a technique to increase the reliability of protection systems. It increases system stability and can prevent large contingencies such as cascading outages and blackouts. This paper describes how POWER DIFFERENTIAL protection (PDP) can be used within a WAP and shows that the algorithm operates correctly for all types of system faults whilst preventing unwanted tripping, even if the data has been distorted by CT saturation or by data mismatches caused by delays in theWAP data collection system. The PDP algorithm has been simulated and tested on an Iranian 400kV transmission line during different fault and system operating conditions. The proposed operating logic and the PDP algorithm were also evaluated using simulation studies based on the Northern Ireland Electricity (NIE) 275 kV network. The results presented illustrate the validity of the proposed protection.

Elliptic curve cryptography (ECC) is one of the most popular public key systems in recent years due to its both high security and low resource consumption. Thus, ECC is more appropriate for Internet applications of Things, which are mainly involved with limited resources. However, non-invasive side channel attacks (SCAs) are considered as a major threat to ECC systems. In this paper, we design a processor for the ECC in the binary field, resistant to DIFFERENTIAL POWER attacks ((DPA)). The main operations in this architecture are randomized Montgomery multiplication and division units, which make it impossible to create (DPA)s by involving a random number in the calculation process. The goal is to accelerate the operation by opening the loops in the Montgomery randomized multiplication/division units, and accordingly, bit-parallel design instead of bit serial design. The results show that, despite the complexity of the logic in the two/three-bit processing versions, the speed is significantly improved by accepting a slight increasing in the area resource. Further, our design is flexible where in the top-level module, depending on the area-speed trade-off, a variety of multiplier and divisor units can be selected. The FPGA evaluations show that in terms of Time×Slice metric, the 2-bit divider/3-bit multiplier version of our architecture leads to 40% improvement over the best previous work. Further, by duplicating the divider and multiplier modules along the bit-parallel architecture this gain can reach to 50%. In terms of operation speed, our design versions are faster than previous work by a factor of 1. 87 and 3. 29. Furthermore, ASIC evaluations in term of Time×Area metric, indicate that deploying 2-bit multiplier leads to 19% gain relative to previous well-known work. Moreover, duplication of modules along with bit-paralleling amplifies the overall gain up to 36%.

Side-channel attacks are considered to be the most important problems of modern digital security systems. Today, DIFFERENTIAL POWER Attack ((DPA)) is one of the most POWERful tools for attacking hardware encryption algorithms in order to discover the correct key of the system. In this work, a new scheme based on randomizing POWER consumption of a fixed-operation logic gate is proposed. The goal of this method is enhancing the immunity of AES algorithm against (DPA). Having a novel topology to randomize the POWER consumption of each Exclusive-NOR gate, the proposed circuit causes random changes in the overall POWER consumption of the steps of the algorithm; thus, the correlation between the instantaneous POWER consumption and the correct key is decreased and the immunity of the AES implementations which the key is injected into their process through Exclusive-NOR gates is extremely increased. The proposed method can be used as a general hardening method in the majority of cryptographic algorithms. The results of theoretical ANALYSIS and simulations in 90-nm technology demonstrate the capability of the proposed circuits to strengthen AES against (DPA). The CMOS area and POWER consumption overhead is less than 1%.

In this paper, a novel risk-based, two-objective (technical and economical) optimal reactive POWER dispatch method in a wind-integrated POWER system is proposed which is more consistent with operational criteria.  The technical objective includes the minimization of the new voltage instability risk index. The economical objective includes cost minimization of reactive POWER generation and active POWER loss. The proposed voltage instability risk employs a hybrid possibilistic (Delphi-Fuzzy)-probabilistic approach that takes into consideration the operator’s experience, the wind speed and demand forecast uncertainties when quantifying the risk index. The decision variables are the reactive POWER resources of the system. To solve the problem, the modified multi-objective particle swarm optimization algorithm with sine and cosine acceleration coefficients is utilized. The method is implemented on the modified IEEE 30-bus system. The proposed method is compared with those in the previously published literature, and the results confirm that the proposed risk index is better at estimating the voltage instability risk of the system, especially in cases with severe impact and low probability. In addition, according to the simulation results compared to typical security-based planning, the proposed risk-based planning may increase the security and economy of the system due to better utilization of system resources.

2,2’ -Dipyridylamine, H(DPA), reacts with NaH or MeLi in THF and generates the sodium or lithium salt (Na(DPA) or Li(DPA)) respectively. Futher reaction of [Cu(TMEDA)2] [CuCl2] (TMEDA=tetramethylethylenediamine) with one equivalent of this ligand in THF leads to the formation of a yellow dimeric Cu(I) complex, [Cu((DPA))2]. Analytical data, molecular weight, and magnetic susceptibility measurements, confirm the formula [Cu((DPA))]2.